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为产生一个与视频信号中的行同步信号严格同步的时钟信号,设计了一种数模混合结构的电荷泵锁相环(PLL)电路。通过对锁相环电路中鉴频鉴相器、电荷泵电路、振荡器电路设计适当改进,实现了性能稳定的时钟信号。采用中芯国际公司的0.35μm 2P4M双层多晶硅四层金属3.3 V标准CMOS工艺,使用Simulink软件进行了系统级仿真、Spectre软件进行了电路级仿真、Hsim软件进行了混合仿真。结果表明,环路输出频率27 MHz时钟信号,占空比达到50.141%,输入最大2 Gbit/s像素信号条件下,时钟抖动小于350 ps,锁定时间小于30μs,芯片的工作达到设计要求。
To produce a clock signal that is strictly synchronized with the line sync signal in the video signal, a charge-pump phase-locked loop (PLL) circuit with a mixed digital-analog structure is designed. Through the phase-locked loop circuit in the phase-frequency detector, charge pump circuit, oscillator circuit design appropriate improvements to achieve a stable performance of the clock signal. The SMIC 0.35μm 2P4M double-layer polysilicon four-layer metal 3.3V standard CMOS process was used to simulate the system level using Simulink software. The specter software was used to simulate the circuit level and the Hsim software was mixedly simulated. The result shows that the duty cycle of the 27 MHz clock signal reaches 50.141% and the clock jitter is less than 350 ps and the lock time is less than 30 μs under the input of 2 Gbit / s pixel signal. The design of the chip meets the design requirements.