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本文表明,Si-SiO_2界面过渡层中的载流子陷阱对硅体内电子存在慢俘获作用,这将导致npn型双极晶体管电流放大系数h_(FE)随时间的正向漂移。从这种物理机制出发,建立了相应的数学模型。经计算机模拟分析,求得了h_(FE)随时间的漂移曲线以及温度、发射结偏压、基区表面势对这种漂移的影响。结果表明,基区表面势对漂移量的大小有重要影响,高温老化是漂移失效筛选的有效手段。
This paper shows that the carrier traps in Si-SiO_2 interfacial transition layer have a slow trapping effect on the electrons in silicon body, which will cause the current amplification factor h_ (FE) of npn-type bipolar transistor to drift forward with time. Starting from this physical mechanism, a corresponding mathematical model is established. After computer simulation, the drift of h_ (FE) over time and the influence of temperature, emitter junction bias and base surface potential on the drift were obtained. The results show that the surface potential of the base area has an important influence on the amount of drift, and high temperature aging is an effective method for screening drift failure.