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Efficient reconfigurable field programmable gate array (FPGA) architectures for the MD6-224/256/384/512 Hash algorithm are proposed in this article. The basic iterative compact design requires 923 ALMs and achieves a throughput ranging from 225 Mbit/s to 394 Mbit/s at a maximum frequency of 198 MHz. The 32-step-unrolled high-throughput design requires 7 090 ALMs and achieves a throughput ranges from 5 776 Mbit/s to 9 490 Mbit/s at a maximum frequency of 173 MHz. The simulation results show that high flexibility and efficient FPGA implementation of the MD6 Hash function is achieved.
Efficient reconfigurable field array (FPGA) architectures for the MD6-224 / 256/384/512 Hash algorithm are proposed in this article. The basic iterative compact design requires 923 ALMs and achieves a throughput ranging from 225 Mbit / s to 394 Mbit / s at a maximum frequency of 198 MHz. The 32-step-unrolled high-throughput design requires 7,090 ALMs and achieves a throughput range from 5,776 Mbit / s to 9,490 Mbit / s at a maximum frequency of 173 MHz. simulation results show that high flexibility and efficient FPGA implementation of the MD6 Hash function is achieved.