描述了一种高性能CMOS线阵 2 88× 4读出电路的设计。该读出电路是一个大规模混合信号电路 ,集成了时间延迟积分以提高信噪比 ,实现了缺陷像素剔除以提高阵列的可靠性。其他特征包括积分时间可调 ,多级增益 ,双向扫描 ,超采样 ,以及内建电测试。该芯片采用 1 2 μm双层多晶硅双层金属CMOS工艺。测量得到的总功耗约为 2 4mW ,工作电压 5V。 Describes the design of a high performance CMOS linear 2 88 × 4 readout circuit. The readout circuit is a large-scale mixed-signal circuit that integrates time delay integration to improve signal-to-noise ratio and achieve defective pixel rejection to improve the reliability of the array. Other features include adjustable integration time, multi-level gain, bi-directional scanning, oversampling, and built-in electrical testing. The chip uses a 1 2 μm double-layer polysilicon double-metal CMOS process. The measured total power consumption is about 24mW, operating voltage 5V.