论文部分内容阅读
本设计是采用FPGA来实现E1通信协议,主要实现的功能有支持E1单帧和复帧方式、CRC4校验、可选时隙、多种告警管理、CAS复帧的传输、多种环回测试功能、Sa比特处理器及支持接收通路时钟的提取与锁定;满足E1输出接口时序的抖动特性。利用FPGA的硬件可定制性特点可以对E1协议的各个部分做特殊处理来满足不同的需求,外部只需增加简单的电平转换电路即可实现整个E1通信系统,这使得比传统的E1通信系统(专用芯片方案)有更强的竞争优势。
The design is the use of FPGA to achieve E1 communication protocol, the main functions are to support E1 single and multi-frame mode, CRC4 parity, optional time slots, a variety of alarm management, CAS multi-frame transmission, a variety of loopback test Function, Sa bit processor and support receive path clock extraction and locking; to meet the E1 output interface timing jitter characteristics. The use of FPGA hardware customizable features of the various parts of the E1 protocol can do special treatment to meet different needs, simply add a simple external level conversion circuit to achieve the entire E1 communication system, which makes the traditional E1 communication system (Dedicated chip program) have a stronger competitive advantage.