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本文提出了一种新型的可变ｒａｄｉｘ快速乘法硬件算法，算法中，采用了二进制数的冗余数表示方法，使二个大数（大到５１２ｂｉｔ位或更大）的相加在Ｏ（１）时间内完成而无需等待进位；其次，提出了可变ｒａｄｉｘ快速乘法思想，使算法比ｒａｄｉｘ－４的乘法算法速度提高３３％，比ｒａｄｉｘ－８的乘法算法速度提高１１％而硬件实现更为简单，算法还能克服在较坏和最坏条件下，ｒａｄｉｘ－８乘法算法速度严重下降的缺陷，是一种可以作为核心运算有效地使用在许多公钥密码体制（如ＲＳＡ）硬件ＶＬＳＩ实现中的新型快速算法。
This paper presents a new variable radix fast multiplication hardware algorithm, the algorithm uses a binary number representation of the redundant number, so that two large numbers (up to 512 bits or more) in the O (1 ) Is completed within the time without waiting for the carry. Secondly, the idea of variable radix fast multiplication is proposed, which makes the algorithm speed up 33% faster than radix-4 multiplication algorithm and 11% faster than the radix-8 multiplication algorithm, Simpler, the algorithm can also overcome the drawback of the radix-8 multiplication algorithm being severely degraded at worst and worst case conditions and is a core VLSI implementation that can effectively be used in many public-key cryptosystem (eg, RSA) hardware VLSI implementations New fast algorithm.