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实现了一种通过FPGA来扩展微处理器SEP3203的PS/2接口的软硬件结合的方法.嵌入式处理器模拟出的I/O口时序受到各种因素的影响,纯软模拟结果无法保证符合PS/2传输协议,这将增加编程的复杂度,并且破坏程序的可移植性.通过软件和FPGA的结合,保证了PS/2接口收发数据的精确性和可移植性,并为上层提供了PS/2接口的嵌入式系统驱动.经过在PC机上ARM ADS软件环境下测试,响应延时小于200μs,完全符合协议标准.
A method of combining hardware and software of PS / 2 interface of microprocessor SEP3203 is realized by FPGA.The timing of I / O port simulated by embedded processor is affected by various factors and the result of pure soft simulation can not be guaranteed PS / 2 transfer protocol, which will increase the complexity of programming, and undermine the portability of the program through the combination of software and FPGA to ensure that the PS / 2 interface to send and receive data accuracy and portability, and provided for the upper PS / 2 interface embedded system driver.After ADS software environment on the PC test machine, the response delay is less than 200μs, in full compliance with the protocol standard.