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HT-7装置运行期间,必须有一个控制机制来协调各子系统,使它们按照预定的时序工作,总控时序系统统一提供触发和时钟信号。本文阐述了基于VXI总线的总控时序系统在HT-7实验装置中的功能及应用和基于VXI总线的总控时序系统的硬件构成。最后介绍了触发模块的技术升级,采用新的FPGA芯片,设计出32位数据线的新模块,给出了新模块的仿真结果。升级后的模块简化了电路,获得了更宽的时间控制量。
During operation of the HT-7 device, a control mechanism must be provided to coordinate the subsystems so that they operate at a predetermined timing. The master timing system provides a uniform trigger and clock signal. This article describes the VXI bus based control timing system in the HT-7 experimental device functions and applications and VXI bus based control timing system hardware. Finally, it introduces the technology upgrade of the trigger module, adopts the new FPGA chip, designs a new module of 32-bit data line, and gives the simulation result of the new module. The upgraded module simplifies the circuit, gaining a wider amount of time control.