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基于整数分频锁相环结构实现的时钟发生器,该时钟发生器采用低功耗、低抖动技术,在SMIC 65 nm CMOS工艺上实现。电路使用1.2 V单一电源电压,并在片上集成了环路滤波器。其中,振荡器为电流控制、全差分结构的五级环形振荡器。该信号发生器可以产生的时钟频率范围为12.5～800MHz,工作在800 MHz时所需的功耗为1.54 mW,输出时钟的周期抖动为:pk-pk=75 ps,rms=8.6 ps;Cycle-to-Cycle抖动为:pk-pk=132 ps,rms=14.1 ps。电路的面积为84μm2。
A clock generator based on an integer-fractional PLL architecture that uses low power, low jitter technology implemented on the SMIC 65 nm CMOS process. The circuit uses a single 1.2 V supply voltage and integrates a loop filter on-chip. Among them, the oscillator is a current controlled, fully differential five-stage ring oscillator. The clock generator can generate a clock frequency range of 12.5 to 800 MHz and consumes 1.54 mW at 800 MHz. The output clock cycle jitter is: pk-pk = 75 ps, rms = 8.6 ps; Cycle- The to-Cycle jitter is: pk-pk = 132 ps, rms = 14.1 ps. The area of the circuit is 84μm2.