基于台积电TSMC 0.35μm 3.3V标准半导体工艺,完成一款低电压、超低功耗人工耳蜗植入体芯片设计与流片.首先,基于目标工艺设计一套2.0V低电压标准单元库,完成电路结构设计、特征化提取和版图设计;其次,以2.0V低电压标准单元库为目标工艺库,完成植入体芯片综合及物理设计,引入基于蒙特卡罗仿真的统计静态时序分析方法,提高低电压路径的时序收敛性.测试结果显示:当工作电压由3.3V降至2.0V时,人工耳蜗植入体芯片功能正常,全芯片功耗下降了74.7%. Based on the TSMC 0.35μm 3.3V standard semiconductor technology from TSMC, a low-voltage, ultra-low-power cochlear implant chip design and flow sheeting is completed.Firstly, based on the target technology, a set of 2.0V low voltage standard cell library is designed to complete the circuit Structure design, feature extraction and layout design. Secondly, the standard cell library of 2.0V low voltage is taken as the target technology library to complete the synthesis and physical design of the implant chip. The statistical static timing analysis method based on Monte Carlo simulation is introduced to improve the low The results show that when the operating voltage is reduced from 3.3V to 2.0V, the cochlear implant chip functions normally and the power consumption of the whole chip decreases by 74.7%.