论文部分内容阅读
ＶＬＳＩ电路芯片集成度的不断增加，使得设计趋于复杂化，这就对版图验证工具的处理能力与性能提出了进一步的要求。运用特殊的硬件将版图验证的某些算法固化，利用其中内在的并行性来获得处理速度的提高是一类非常有效的方法。本文提出了一种用于在版图验证算法中得到广泛运用的线扫描算法中边排序操作的硬件实现。并且在ＦＰＧＡ上进行了验证，整个系统实现于一块ＰＣ机的扩展卡上。测试的结果表明，对于排序的操作，硬件实现的速度要比软件快一个数量级。
VLSI circuit chip integration continues to increase, making the design more complicated, which on the layout verification tools, processing power and performance put forward further requirements. It is a very effective way to solidify certain algorithms of layout validation using special hardware and to increase the processing speed by using the inherent parallelism. This paper presents a hardware implementation of the side-by-side operation of a line scan algorithm that is widely used in layout verification algorithms. And verified in the FPGA, the entire system is implemented in a PC expansion card. The test results show that, for the sort operation, the hardware to achieve faster than the software an order of magnitude.