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介绍了用于±50 Mvar链式静止无功发生器(STATCOM)的基频优化脉宽调制(PWM)的脉冲发生器。根据链式逆变器电路结构的特点制定了基频优化PWM方案。脉冲发生器采用数字信号处理器(DSP)加现场可编程逻辑门阵列(FPGA)作为主要的处理器,根据两者各自的特点分配功能,提高了脉冲发生器的总体性能。该脉冲发生器在20 kVA链式STATCOM原理样机中可靠运行,实验结果证明了设计的正确性。
Introduced a fundamental frequency optimized pulse width modulation (PWM) pulse generator for a ± 50 Mvar chain static var generator (STATCOM). According to the characteristics of the chain inverter circuit structure to develop a fundamental frequency PWM optimization program. The pulse generator uses a digital signal processor (DSP) plus field programmable gate array (FPGA) as the main processor, which allocates functions according to their respective characteristics and improves the overall performance of the pulse generator. The pulse generator operates reliably in a 20 kVA chain STATCOM prototype and the experimental results demonstrate the correctness of the design.