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基于IBM公司的0.18μm RF SOI CMOS工艺,设计了一款应用于S波段的高线性低功耗低噪声放大器。在传统共源共栅拓扑结构的基础上,本文提出使用有源偏置电路、级间匹配网络和并联反馈结构,使设计的放大器具有噪声低、线性度高和功耗小等特点。仿真结果表明,该放大器在2.3~2.7 GHz频段,电源电压为1.8 V,功耗为9.8 mW的条件下,噪声系数小于0.8 dB,增益大于14 dB,输入回波损耗和输出回波损耗均大于10 dB,隔离度大于27 dB,输入三阶交调截取点大于15 dBm,满足无线基础架构接收器对低噪声放大器的所有性能要求。
Based on IBM’s 0.18μm RF SOI CMOS process, a high linearity, low power, low noise amplifier designed for the S-band is designed. Based on the traditional cascode topology, this paper proposes the use of an active bias circuit, an inter-stage matching network and a parallel feedback structure to make the amplifier designed with low noise, high linearity and low power consumption. The simulation results show that the noise figure is less than 0.8 dB, the gain is greater than 14 dB, the input return loss and the output return loss are both greater than 2.3 dB in the frequency band of 2.3 ~ 2.7 GHz, the power supply voltage is 1.8 V and the power consumption is 9.8 mW 10 dB, greater than 27 dB of isolation, and greater than 15 dBm of third-order intercept input, meeting all performance requirements for low-noise amplifiers in wireless infrastructure receivers.