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图1所示的倍频电路仅用了一片集成电路。和其它倍频电路一样,该电路也利用输入信号的上跳沿和下跳沿来产生数字脉冲。这样,就有效地将输入信号倍频了。在IC_1的输入端如果没有RC网络,IC_1就不能产生任何输出脉冲。然而,由于加入一些RC网络就使输入信号的一个沿相对于另一沿延时了。对于上跳沿,IC_1的A输入滞后B输入,而对于负跳沿,IC_1的B输入滞后A输入。这样,改变R_3就可以使输出脉冲的占空比从0到100%可调。IC_1的最小输出脉冲宽度决定了该电路的最高频率。
The frequency multiplier circuit shown in Figure 1 only uses one integrated circuit. Like other frequency multiplier circuits, the circuit also uses the upper and lower edges of the input signal to generate a digital pulse. In this way, the input signal is effectively doubled. IC_1 can not generate any output pulses without the RC network at the input of IC_1. However, one edge of the input signal is delayed relative to the other due to the addition of some RC networks. For the upper edge, the A input to IC_1 lags the B input, and for negative edges, the B input to IC_1 lags the A input. In this way, changing R_3 will make the duty cycle of the output pulse adjustable from 0 to 100%. The minimum output pulse width of IC_1 determines the maximum frequency of the circuit.