A fractional-N frequency synthesizer for wireless sensor network nodes

来源 :Journal of Semiconductors | 被引量 : 0次 | 上传用户:p_pppoe
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This paper presents a fractional-N frequency synthesizer for wireless sensor network(WSN) nodes. The proposed frequency synthesizer adopts a phase locked loop(PLL) based structure, which employs an LC voltagecontrolled oscillator(VCO) with small VCO gain(KVCO) and frequency step(fstep) variations, a charge pump(CP)with current changing in proportion with the division ratio and a 20-bit △∑ modulator, etc. To realize constant KVCO and fstep, a novel capacitor sub-bands grouping method is proposed. The VCO sub-groups’ sizes are arranged according to the maximal allowed KVCOvariation of the system. Besides, a current mode logic divide-by-2 circuit with inside-loop buffers ensures the synthesizer generates I/Q quadrature signals robustly. This synthesizer is implemented in a 0.13 m CMOS process. Measurement results show that the frequency synthesizer has a frequency span from 2.07 to 3.11 GHz and the typical phase noise is 86:34 dBc/Hz at 100 k Hz offset and 114:17 dBc/Hz at 1 MHz offset with a loop bandwidth of about 200 k Hz, which meet the WSN nodes’ requirements. The proposed paper presents a fractional-N frequency synthesizer for wireless sensor network (WSN) nodes. The proposed frequency synthesizer adopts a phase locked loop (PLL) based structure, which employs an LC voltage controlled oscillator (VCO) with small VCO gain frequency step (fstep) variations, a charge pump (CP) with current changing proportion with the division ratio and a 20-bit ΔΣ modulator, etc. To realize constant KVCO and fstep, a novel capacitor sub-bands grouping method is proposed . The VCO sub-groups’ sizes are arranged according to the maximal allowed KVCOvariation of the system. Besides, a current mode logic divide-by-2 circuit with inside-loop buffers ensures the synthesizer generates I / Q quadrature signals robustly. This synthesizer is implemented in a 0.13 m CMOS process. Measurement results show that the frequency synthesizer has a frequency span from 2.07 to 3.11 GHz and the typical phase noise is 86:34 dBc / Hz at 100 k Hz offset and 114: 17 dBc / Hz at 1 MHz offse t with a loop bandwidth of about 200 k Hz, which meets the WSN nodes’ requirements.
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