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这里报导的几种控制电路可以决定锁相环的上、下频限和离散的连续频段的个数。在控制电路中,锁相环的除 N 计数器接在 BCD(二一十进制加法器)加法器的输出端,BCD 的第一组输入接在 BCD 开关上,用以决定合成器输出信号的频率下限。扫描时钟电路驱动的十进计数器接在加法器的另一组输入端,可以有选择地递增除 N 计数器的 N。用可编程序的逻辑电路监控十进计数器的输出信号以控制离散频段的个数。另一个可编程序的逻辑电路监控 BGD 加法器的输出以控制合成器输出信号的频率上限。此外 BCD 加法器加上转换开关就能输出更多的频段数。
Several control circuits reported here determine the upper and lower frequency limits of the PLL and the number of discrete continuous frequency bands. In the control circuit, the phase-locked loop divider N counter is connected to the BCD (binary adder) adder output, the first set of BCD input BCD switch to determine the output signal of the synthesizer Lower limit of frequency. The scan clock circuit driven decimator is connected to the other input of the adder and optionally increments N except the N counter. Programmable logic circuits monitor the output signal of the decimator to control the number of discrete frequency bands. Another programmable logic circuit monitors the output of the BGD adder to control the upper frequency limit of the synthesizer output signal. In addition BCD adder plus the switch can output more number of bands.