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本文描述双极数字电路逻辑模拟的一种新方法。该方法是以晶体管开关电平模型的发展和用开关图表示电路为基础的。它自动地把电路划分为子电路,然后根据子电路的输入和初始条件表示的结点逻辑状态产生符号逻辑表达式。因此,该法从晶体管网络表或布局中提出了一个门级功能描述。利用求得的逻辑表达式或开关图模型能够完成逻辑和故障模拟。该法对共模逻辑(CML)双极电路设计的逻辑模拟已用计算机程序实现。
This article describes a new approach to logic simulation of bipolar digital circuits. The method is based on the development of the transistor switching level model and the switching diagram representation of the circuit. It automatically divides the circuit into sub-circuits, and then generates symbolical logic expressions based on the sub-circuit’s inputs and the logic states of the nodes represented by the initial conditions. Therefore, the law from the transistor network table or layout proposed a gate-level functional description. Logic and fault simulation can be done using the obtained logical expression or switch diagram model. This method of logic simulation of CML bipolar circuit design has been implemented with a computer program.