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提出一个改进的二阶三位噪声耦合过采样调制器,它将量化器前所有的加法运算移动到第2个积分器的前面,并通过引入反馈通道和延时输入信号,使反馈数模转换器的苛刻时序得到缓解。此调制器在0.35μmCMOS工艺下设计并生产,整个调制器使用了两个有源模块。在100 kHz信号带宽和12.8 MHz时钟频率下,完成了86.4 dB的SNDR和95.8 dB的DR,3.3 V电源电压下,消耗9.84 mW。此调制器能满足GSM系统的需求。
An improved second-order, three-bit, noise-coupled oversampling modulator is proposed which moves all the adders before the quantizer to the front of the second integrator and converts the feedback digital-to-analog The harsh timing of the device has been alleviated. The modulator is designed and fabricated in a 0.35μm CMOS process and uses two active modules throughout the modulator. A SNDR of 86.4 dB and a DR of 95.8 dB were achieved with a 100 kHz signal bandwidth and a 12.8 MHz clock frequency, consuming 9.84 mW at a 3.3 V supply voltage. This modulator can meet the needs of the GSM system.