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研究了在低温时用超高真空升华方法沉积的均匀外延硅膜和结的结构及电特性。对硼和磷掺杂硅源升华的外延层扩展电阻的测定表明,外延膜的可沉积杂质浓度一定且均匀。在(111)晶面(在温度650℃以上)和(100)晶面(在温度低于500℃时)已生成无层错外延层。已获得极为良好的硅结结构,其生长温度大大地低于已报导的在1.5Ω-cm N型(100)衬底上外延电阻率达0.05Ω-cm的P型硅所构成的结的生长温度。一股说来,这些结显示出突变杂质分布的横截面,其特点是反向漏泄电流低、电压击穿极高,接近由所测电阻率算出的理论击穿电压。用载流子衰减技术测得少数载流子寿命是4至8μsec。衬底外扩散(为沉积前清洗衬底表面的高温所致)的不利影响,可用连续沉积整个外延结结构的方法避免。在N型外延结构上具有良好结特性的P~+N~-结已用浓P和淡N掺杂源成功地形成。
The structure and electrical properties of uniform epitaxial silicon films and junctions deposited by ultra-high vacuum sublimation at low temperature were investigated. Measurement of epitaxial layer extension resistance of sublimation of boron and phosphorus-doped silicon sources shows that the deposi- tive impurity concentration of epitaxial films is constant and uniform. A layer-free epitaxial layer has been formed on the (111) crystal plane (at a temperature above 650 ° C) and the (100) crystal plane (at a temperature below 500 ° C). A very good silicon junction structure has been obtained whose growth temperature is significantly lower than the reported growth of junctions made of P-type silicon having an epitaxial resistivity of 0.05 Ω-cm on a 1.5 Ω-cm N type (100) substrate temperature. In summary, these junctions show a cross-section of abrupt impurity distribution, characterized by low reverse leakage current and extremely high voltage breakdown close to the theoretical breakdown voltage calculated from the measured resistivity. The minority carrier lifetime measured by carrier-drop techniques is 4 to 8 μsec. The adverse effects of out-of-substrate diffusion (caused by the high temperature of the cleaned substrate surface prior to deposition) can be avoided by continuously depositing the entire epitaxial junction structure. P ~ + N ~ - junctions with good junction properties on the N - type epitaxial structure have been successfully formed with concentrated P and light N doping sources.