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图中所示的分频器可以把输入脉冲的频率进行2～50倍以内的任意整数倍分频。但输入脉冲应具有TTL逻辑电平,其频率不超过100千赫。分频器的输出脉冲最低频
The divider shown in the figure can divide the frequency of the input pulse by an integral multiple of 2 ~ 50 times. However, the input pulse should have a TTL logic level and its frequency does not exceed 100 kHz. Divider output pulse lowest frequency