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本文描述了一种32×32位快速并行结构乘法器,介绍了基于修正布斯编码算法的部分积产生电路,并对部分积的符号扩展进行了简化。给出了基于4∶2压缩器的华莱士树的实现方法,在最后的快速进位链中采用64位快速超前进位加法器以提高乘法器的运行速度。并用PSPICE仿真工具对其进行了功能验证和仿真。通过仿真分析比较,该32×32位乘法器的速度比传统的32位基于Wallace/Dadda的乘法器的速度快18.9%。
In this paper, a 32 × 32-bit fast parallel architecture multiplier is introduced. The partial product generation circuit based on the modified Booth coding algorithm is introduced, and the sign extension of partial products is simplified. The implementation of the Wallace tree based on the 4: 2 compressor is given. A 64-bit fast run-ahead adder is used in the last fast carry chain to increase the multiplier’s speed. And use PSPICE simulation tools to verify the function and simulation. Through simulation analysis and comparison, the 32 × 32-bit multiplier is 18.9% faster than the traditional 32-bit Wallace / Dadda-based multiplier.