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日本NTT研究所通过采用WSiN包封退火法,用以提高杂质分布形状的可控性;采用lu/WSiN两层栅电极结构,将栅电阻降低到原来的1/200(3μQ·cm);采用隐埋p型层技术,使亚微米栅长FET的衬底泄漏电流得
Japan NTT Institute by using WSiN encapsulation annealing method to improve the controllability of the impurity distribution shape; using lu / WSiN two gate electrode structure, the gate resistance is reduced to the original 1/200 (3μQ · cm); using Buried p-type layer technology, so that sub-micron gate FET substrate leakage current too