对一种 CMOS/ SOI6 4Kb静态随机存储器进行了研究 ,其电路采用 8K× 8的并行结构体系 .为了提高电路的速度 ,采用地址转换监控 ( Address- Translate- Detector,ATD)、两级字线 ( Double- Word- L ine,DWL)和新型的两级灵敏放大等技术 ,电路存取时间仅 40 ns;同时 ,重点研究了 SOI静电泄放 ( Electrostatic- Discharge,ESD)保护电路和一种改进的灵敏放大器 ,设计出一套全新 ESD电路 ,其抗静电能力高达 42 0 0— 45 0 0 V.SOI6 4KbCMOS静态存储器采用 1.2 μm SOI CMOS抗辐照工艺技术 ,芯片尺寸为 7.8m m× 7.2 4mm A kind of CMOS / SOI6 4Kb static random access memory is studied, and the circuit adopts 8K × 8 parallel architecture.In order to improve the speed of the circuit, this paper uses Address-Translate-Detector (ATD) Double-Word-Linear (DWL) and new two-stage sensitive amplification technology, the circuit access time is only 40 ns; the same time, focusing on the SOI Electrostatic Discharge (ESD) protection circuit and an improved Sensitive amplifier designed a new ESD circuit, the antistatic capacity of up to 42 0 0- 45 0 0 V. SOI6 4KbCMOS static memory using 1.2 μm SOI CMOS radiation technology, the chip size of 7.8mm × 7.2 4mm