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提出了基于有限域运算单元的柔性AES加密系统。通过对不同密钥扩展的算法进行比较分析,利用其基本运算单元相同的特性,采用控制单元实现可支持128位、192位和256位三种密钥长度的柔性结构。采用集成化的可重构柔性AES加密系统,可以降低硬件逻辑资源消耗。使用Verilog HDL硬件语言进行仿真,并在0.35μm工艺下进行逻辑综合。结果表明,时钟频率可达180 MHz,对于128位密钥长度,系统吞吐量可达2.11 Gbps。
A flexible AES encryption system based on finite field computing unit is proposed. By comparing and analyzing the algorithm of different key expansion, the control unit is used to realize the flexible structure which can support the key lengths of 128 bits, 192 bits and 256 bits by using the same characteristics of its basic operation unit. An integrated, reconfigurable, flexible AES encryption system reduces hardware logic resource consumption. Emulated in the Verilog HDL hardware language and integrated logically in a 0.35μm process. The result shows that the clock frequency can reach 180 MHz and the system throughput can reach 2.11 Gbps for a 128-bit key length.