在超大规模集成电路(VLSI)习惯设计中,很困难和消耗时间的工作是以逻辑设计转换成版面图的工作。有一种排列标准逻辑单元的方法,具有相对讲执行容易但硅片面积很浪费,而用手工堆集布局具有很高的器体堆集密度实现自动化是困难的。 本报告将讨论以多晶硅栅为工艺,作为CMOS VLSI设计图样的门矩阵。藉助于用一种有秩序的结构,即其特点为具有多晶硅作行和扩散条作列的一个矩阵,探讨简化和统一设计的程序。相信这种图样可直接应用到NMOS工艺。门矩阵被认为是Weinberger设计图解的综合。该图样在金属栅工艺中是对于PMOS与非门(NAND)栅的发展。对于母线(bus-structurud)逻辑,如微处理机CPUS指出,门矩阵比(?)虑到器件堆集密度 In VLSI customary designs, the difficult and time-consuming task of converting from logical design to layout. There is a method of arranging standard logic cells, which is relatively easy to implement but has a waste of silicon area, but it is difficult to automate with a high stack density of devices by manual stacking. This report will discuss polysilicon gate technology as a gate matrix for CMOS VLSI design patterns. A simplified and uniform design procedure is explored by using an ordered structure that is characterized by a matrix of rows and stripes of polysilicon. I believe this pattern can be applied directly to the NMOS process. The gate matrix is ​​considered as a synthesis of Weinberger’s design schemas. This pattern is a development of PMOS and NAND gates in metal gate processes. For bus-structurud logic, such as Microprocessor CPUS, the gate matrix ratio (?) Takes into account the device packing density