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本文首先介绍了采用J-K触发器,使用卡诺化简法设计同步计数器的步骤.其次,着重介绍了在绝大多数教科书及工程设计中往往不注意的一个问题,即当进位基数N小于计数器的状态数2n(n为计数器的级数)时,在不用的状态中有可能出现计数“陷阱”,以及检查设计是否正确和有无计数“陷阱”的方法.并对无“陷阱”(公式<1>及图3)及有“陷阱”(公式<2>及图6)的情况进行了电路试验,证明了理论分析是正确的。最后,列出级进位制同步计数器的输入方程,以供设计者录用。
This article first introduces the steps of using JK flip-flop and Kano simplification method to design synchronous counter.Secondly, it focuses on one of the problems that most textbooks and engineering design often do not pay attention to, that is, when the base N is less than the counter When the number of states is 2n (n is the number of counters), there is a possibility of counting “traps” in unused states, and checking whether the design is correct and counting “traps” 1> and Figure 3) and the “trap” (Equation <2> and Figure 6) conducted a circuit test, the proof of the theoretical analysis is correct. Finally, list the input equations for the progressive-phase synchronization counter for use by the designer.