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基于运用EDA技术,以FPGA器件为核心,用Verilog HDL硬件描述语言来设计各个功能模块,采用DDS直接数字频率合成技术设计信号发生器,通过CPU控制每个采样点的输出间隔来控制输出波形的频率,改变波形存储器中的波形数据来产生任意波形。
Based on the use of EDA technology, FPGA devices as the core, using Verilog HDL hardware description language to design various functional modules, using DDS direct digital frequency synthesis technology design signal generator, the output of each sampling point by the CPU control output waveform interval Frequency, change the waveform data in the waveform memory to generate arbitrary waveform.