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本发明的主要目的是提供一种低相位噪声的数字式分频器。包含有选通门(20)的分频器如图1所示。选通门(20)以所需要的分频比选通来自信号源(14)的参考信号的半波脉冲或半周期,并加至放大器(15)。分频比由分频控制单元(22)控制。选通门起到开关的作用,它把参考信号不需要的部分短路到地。选通门由来自控制单元(22)
The main object of the present invention is to provide a digital divider with low phase noise. The divider that contains the gate (20) is shown in Figure 1. The gating gate (20) gates the half-wave pulse or half-cycle of the reference signal from the signal source (14) at the desired frequency division ratio and applies it to the amplifier (15). The frequency division ratio is controlled by the frequency division control unit (22). The gate acts as a switch that shorts the unneeded portion of the reference signal to ground. Gate from the control unit (22)