描述了用于SDH光纤通信STM-16速率级的2.488Gbit/s时钟和数据恢复电路.该电路采用基于注入式锁相环和D触发器的电路结构,在标准的0.35μmCMOS工艺上实现流片.经过测试,当输入长度为231-1的伪随机序列,数据速率为2.488Gbit/s时,在误码率为10-12的条件下,电路的灵敏度小于20mV.恢复得到的时钟具有2.8ps的均方根相位抖动,在100kHz频偏处的相位噪声为-110dBc/Hz,并具有大于40MHz的捕获范围.5V电源供电时,电路消耗680mW功率.芯片面积为1.49mm×1mm. Describes a 2.488 Gbit / s clock and data recovery circuit for SDH optical communications STM-16 rate class.The circuit uses a circuit architecture based on an injection-type phase-locked loop and a D-flip-flop to enable streaming on a standard 0.35 μm CMOS process After the test, the sensitivity of the circuit is less than 20mV when the error rate of 10-12 is input when the data length is 2.488Gbit / s when the pseudo random sequence with the length of 231-1 is input.The recovered clock has 2.8ps The rms phase noise is -110dBc / Hz at 100kHz offset and has a capture range greater than 40MHz. The circuit consumes 680mW at 5V power supply. The chip area is 1.49mm x 1mm.