This paper describes the partitioning of the set of the Boolean equations generatedby the hardware logic translator and the conversion of the subsets into cube arrays.Subsequent to this,it is aimed:(1)to find out the minimal sets of input variables;(2)tofinish the logic minimization;and(3)to decompose a large logic array into smaller onesto meet the design constraints if necessary.These three problems cart all be reduced to solving the corresponding coveringproblems,which may have considerable scales.This paper gives the method to solvelarge cycling cover tables of these problems with cover-matrix complementation(sharp operation).The salient feature of the method is that it can give the optimalsolutions and need not store the covering matrix.The above work is intended to set up an automatic logic synthesis system totranslate register transfer level language descriptions into hardware logic diagrams. This paper describes the partitioning of the set of the Boolean equations generated by the hardware logic translator and the conversion of the subsets into cube arrays. Subsequent to this, it is aimed at: (1) to find out the minimal sets of input variables; (2 ) tofinish the logic minimization; and (3) to decompose a large logic array into smaller onesto meet the design constraints if necessary. these three problems cart all be reduced to solving the corresponding coveringproblems, which may have applied scales. to solvelarge circulation cover tables of these problems with cover-matrix complementation (sharp operation). The salient feature of the method is that it can give the optimal solution and need not store the covering matrix. above work is intended to set up an automatic logic synthesis system totranslate register transfer level language publications into hardware logic diagrams.