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在实际的高性能定点数字信号处理器(DSP)设计过程中,往往需要设计一个功能复杂的乘累加器。也就是说,乘累加器不光是要同时完成通常所见的带符号数和无符号数的乘加及乘减运算,而且还需要同时完成整数乘加和小数乘加运算,无偏差的舍入运算,饱和等功能。另外,为了解决DSP中数据相关的问题,往往要求乘累加器在单拍完成所有的这些运算,因此很难找到一个高速度低成本的实现方案。文章首先给出了通常的高性能定点DSP中乘累加器所需要完成的功能需求,然后提出并实现了一个16位高性能乘累加器,将其所需要完成的上述各种功能巧妙地整合起来在单拍内完成,而完成所有上述功能只需要3级4押2压缩和一次超前进位的加法运算。该乘累加器采用0.35μm工艺实现,已经嵌入到数字信号处理器中并已经成功应用于实际的工程项目。
In the actual high-performance fixed-point digital signal processor (DSP) design process, often need to design a complex multiplication accumulator. In other words, multiply accumulators are not only required to perform the usual multiply-add and multiply-and-accumulate operations with signed and unsigned numbers, but also to perform integer multiply-add and fractional-add operations, rounding without deviation Computing, saturation and other functions. In addition, to solve the data-related problems in DSPs, it is often required that all these operations be performed in a single shot by the accumulator, making it difficult to find a high-speed, low-cost implementation. The article first gives the general high-performance fixed-point DSP by the accumulator need to complete the functional requirements, and then proposed and implemented a 16-bit high-performance multiply accumulator, the need to complete the various functions described above are skillfully integrated Done in a single shot, and completing all of the above functions requires only 3 levels of 4 compression and 1 advance adder. The multiply accumulator is implemented in a 0.35μm process and has been embedded in digital signal processors and has been successfully used in practical engineering projects.