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研究了高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响.随着栅介质介电常数增大,肖特基源漏(SBSD)SOI MOSFET的开态电流减小,这表明边缘感应势垒降低效应(FIBL)并不是对势垒产生影响的主要机理.源端附近边缘感应势垒屏蔽效应(FIBS)是SBSD SOI MOSFET开态电流减小的主要原因.同时还发现,源漏与栅是否对准,高k栅介质对器件性能的影响也不相同.如果源漏与栅交叠,高k栅介质与硅衬底之间加入过渡层可以有效地抑制FIBS效应.如果源漏偏离栅,采用高k侧墙并结合堆叠栅结构,可以提高驱动电流.分析结果表明,来自栅极的电力线在介电常数不同的材料界面发生两次折射.根据结构参数的不同可以调节电力线的疏密,从而达到改变势垒高度,调节驱动电流的目的.
The effect of high-k gate dielectric on the performance of Schottky source-drain ultrathin SOI MOSFETs has been investigated. As the dielectric constant of the gate dielectric increases, the on-state current of Schottky source-drain (SOBSD) SOI MOSFETs decreases, The effect of edge induced barrier reduction (FIBL) is not the main mechanism that affects the barrier. The induced edge barrier (FIBS) near the source is the main reason for the decrease of the on-state current of SBSD SOI MOSFET.It is also found that the source If the source and drain overlap with the gate, the transition layer between the high-k gate dielectric and the silicon substrate can effectively suppress the FIBS effect.If the source Drain off the gate, the use of high-k side wall combined with the stacked gate structure, can increase the drive current. Analysis results show that the power lines from the grid in the dielectric constant of different material interface occurs twice refraction. According to different structural parameters can adjust the power line Density, so as to achieve the purpose of changing the barrier height, adjusting the drive current.