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为了降低非规则低密度奇偶校验(low-density parity-check,LDPC)码译码算法的复杂度,提出一种适合数字信号处理器(digital signal processor,DSP)实现的低运算复杂度、低误码平台译码的改进算法。该算法校验节点的运算采用修正最小和算法,外信息的更新采用串行方式,既保持了串行和积算法在有限迭代次数下译码门限低的优点,又降低了节点运算复杂度和误码平台。用定点DSP芯片实现的非规则LDPC码译码器的实测结果表明,该算法能以较低的实现复杂度获得低的误码平台和译码门限。
In order to reduce the complexity of low-density parity-check (LDPC) code decoding algorithm, a low computational complexity, low computational complexity and high performance for digital signal processor (DSP) Improvement of decoding error code platform. The algorithm uses the least squares algorithm and algorithm to update the computation of nodes. The serial information is updated in serial format, which not only keeps the advantages of low decoding threshold in the finite number of iterations, but also reduces the computational complexity and Error code platform. The experimental results of an irregular LDPC code decoder implemented with fixed-point DSP chips show that the algorithm can achieve low error-decoding platforms and decoding thresholds with lower implementation complexity.