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介绍了一种 32位对数跳跃加法器结构 .该结构采用 EL M超前进位加法器代替进位跳跃结构中的组内串行加法器 ,同 EL M相比节约了 30 %的硬件开销 .面向该算法 ,重点对关键单元进行了晶体管级的电路设计 .其中的进位结合结构利用 L ing算法 ,采用支路线或电路结构对伪进位产生逻辑进行优化 ;求和逻辑的设计利用传输管结构 ,用一级逻辑门实现“与 -异或”功能 ;1.0 μm CMOS工艺实现的 32位对数跳跃加法器面积为 0 .6 2 mm2 ,采用 1μm和 0 .2 5 μm工艺参数的关键路径延迟分别为 6 ns和 0 .8ns,在 10 0 MHz下功耗分别为 2 3和 5 .2 m W.
A 32-bit log hop adder architecture is introduced, which uses an EL M leading carry adder instead of an in-group serial adder in the carry-skip structure to save up to 30% of hardware overhead compared to EL M. The algorithm focuses on transistor-level circuit design of the key elements, of which the carry-in structure utilizes the L ing algorithm to optimize the logic for generating the pseudo-carry by the branch line or the circuit structure. The design of the summation logic utilizes the structure of the transmission pipe A logic gate to achieve “and - XOR” function; 1.0 μm CMOS technology to achieve 32-bit log hop adder area of 0.62 mm2, using 1μm and 0. 25μm process parameters of the critical path delay were 6 ns and 0.8 ns, respectively, with power consumption of 2 3 and 5 .2 mW at 10 0 MHz respectively.