当今的数字延迟线只能处理比其延迟时间长的脉冲,这一限制使数字延迟线只能应用于占空比接近50%的场合。现有数字延迟线品种有限(每个抽头2～100ns 的延迟),又进一步限制了它们的应用。由标准数字逻辑电路系列组成的单稳态多谐振荡器可以提供较长的延迟时间,但是,这类器件不能保存占空比信息。例如,一个 PWM(脉宽调制)控制电路(图1)必须处理相当长的延迟,同时又必须保存有关输入占空比的信息。这种双通道精密单稳态多谐振荡器的上一半是靠输入信号的上升沿来触发的。输入信号上升沿触发 D 型触发器 IC_(3A),以使 IC_(4A)输入端为低电平。IC_(4A)有一个漏极开路的输出端,输出信号按照 C_1R_1这一时间常数呈指数增长。JC_(1A)将这一输出信号与一个等于67%V_(CC)的直流电压作比较,从而产生一个等于 R_1C_1的、便于换算的延迟时间。比较器 JC_(1A)的输出信号驱动 RS 锁存器(IC_(2B)和 IC_(2C))的置位输入端。这一输出信号 Today’s digital delay lines can only handle pulses longer than their delay, limiting the digital delay line to applications where the duty cycle is close to 50%. The limited number of available digital delay lines (2 to 100 ns delay per tap) further limits their use. Monostable multivibrators, which consist of a family of standard digital logic circuits, provide longer delay times, but such devices do not hold duty cycle information. For example, a PWM (pulse width modulation) control circuit (Figure 1) must handle a significant delay while preserving information about the input duty cycle. The top half of this dual precision monostable multivibrator is triggered by the rising edge of the input signal. The D flip-flop IC_ (3A) is triggered on the rising edge of the input signal so that the IC_ (4A) input is low. IC_ (4A) has an open-drain output that exponentially increases the output signal by the time constant C_1R_1. JC_ (1A) compares this output signal with a DC voltage equal to 67% V_ (CC), resulting in a scaling time equivalent to R_1C_1. The output of comparator JC_ (1A) drives the set inputs of the RS latches (IC_ (2B) and IC_ (2C)). This output signal