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基于预放大锁存快速比较理论,提出了一种新型高速低功耗CMOS比较器的电路拓扑。采用典型的0.35μm/3.3 V硅CMOS工艺模型,用Cadence软件进行模拟仿真,比较器延迟时间为231 ps,比优化前降低了235 ps;其回馈噪声对输入信号和电阻串参考电压产生的毛刺峰值分别为6.35 mV和1.57 mV;电路功耗118.6μW。运用该结构的比较器具有快速过驱动恢复能力,大幅度提高了比较器的速度;能有效抑制其回馈噪声,功耗低,可用于高速低功耗A/D转换器模块的设计。
Based on the theory of fast comparison of pre-amplification latch-up, a novel high-speed low-power CMOS comparator circuit topology is proposed. The typical 0.35μm / 3.3V silicon CMOS process model is simulated with Cadence software. The comparator delay time is 231 ps, which is 235 ps lower than that before optimization. The feedback noise can cause glitches on the input signal and resistor string reference voltage Peak values were 6.35 mV and 1.57 mV respectively; circuit power consumption was 118.6μW. Comparator with this structure has fast overdrive recovery capability, greatly improve the speed of the comparator; can effectively suppress its feedback noise, low power consumption, can be used for high-speed low-power A / D converter module design.