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综述了测量越过典型有源区形貌的多晶硅栅线宽偏差 ,采用光刻模拟程序计算。采用顶层和底层抗反射涂层与否 ,对从 36 5nm曝光的 0 .40 μm到 193nm曝光的 0 .2 2 5 μm范围抗蚀剂成像中所有线宽进行了计算。
The width deviations of polysilicon gate lines over the typical active region morphology are reviewed. Photolithography simulation programs are used to calculate the width deviations. Using the top and bottom anti-reflective coatings or not, all linewidths were calculated for a 0.225 μm range of resist imaging from 36 nm exposure to 0.40 μm to 193 nm exposure.