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设计了一种用于射频系统的低功耗、中速中精度差分输入逐次逼近型(SAR) A/D转换器.采样完成后采用下极板对接的逻辑算法,10位SAR A/D转换器只需9位DAC即可满足其精度要求.DAC阵列采用分段电容结构,节省了芯片面积.比较器采用前置运算放大器加锁存器的结构,达到了同时兼顾速度和精度的要求.该A/D转换器芯片采用GSMC 0.13 μm 1P7M CMOS工艺制造,其核心电路尺寸为500 μm×360μm,采用1.2V的单电源供电.测试结果表明,当采样频率为10 MS/s,输入信号频率为2 MHz时,该SAR A/D转换器达到8.45位的有效精度,总功耗为2.17 mW;当采样频率为5 MS/s,输入信号频率为1 MHz时,该SAR A/D转换器达到8.75位的有效精度,总功耗为2.07 mW.“,”A low power,medium speed and medium resolution successive approximation (SAR) A/D converter with differential analog inputs was proposed for RF system.The algorithm of logic was used by shorting the bottom-plate of capacitors after sampling,so only 9-bit DAC was required to meet the accuracy requirement of 10 bit SAR A/D converter.The DAC array using segmented capacitor array had saved the chip area.A preamplifier and a latch adopted in the dynamic comparator had reached the requirement of both speed and accuracy.Fabricated in GSMC 0.13 μm 1P7M CMOS process,the SAR A/D converter size was 500 μm×360 μm.It was powered by a single 1.2 V supply.Measured results showed that it had an effective number of bits (ENOB) of 8.45 bit and a total power dissipation of 2.17 mW at 2 MHz input signal frequency and 10 MS/s sampling frequency.At 1 MHz input signal frequency and 5 MS/s sampling frequency,it had an ENOB of 8.75 bit and a total power dissipation of 2.07 mW.