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详细介绍了基于130nm工艺的多模卫星导航基带处理SoC芯片的可测性设计,包括边界扫描测试、存储器内建自测试和全速全扫描测试。为了提高测试效率和降低测试成本,还使用了测试压缩技术。实测结果表明,该方案的测试覆盖率最高可达到97.85%,并且实现了近20倍的测试压缩比率。提及的各种测试性设计在实际回片测试中已得到验证,可广泛应用于复杂片上系统设计,具有一定的应用参考价值。
Described in detail the design of the testability of multi-mode satellite navigation baseband processing SoC chips based on 130nm process, including boundary scan test, memory built-in self-test and full-speed full-scan test. In order to improve test efficiency and reduce test costs, test compression technology is also used. The measured results show that the test coverage of the scheme can reach up to 97.85%, and achieve nearly 20 times the test compression ratio. The various test designs mentioned in the actual backplane test have been verified, can be widely used in complex system-on-chip design, with some application reference value.