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针对某型导弹多总线地面测试设备传输数据量大、传输速度高的要求,设计了一种基于乒乓操作的SDRAM控制器作为测试设备数据缓存器。详细介绍了以FPGA为主控器的设计方案,包括SDRAM内部接口设计、数据传输过程以及乒乓操作的实现方法。通过图像发生装置将图像数据发送给测试总线,对控制器功能进行验证,数据读写速率稳定达到125 Mbit/s,证明本控制器具有良好的性能,能够满足多总线地面测试设备的需求。
Aiming at the requirement of transmitting large amount of data and high transmission speed of a certain missile multi-bus ground testing equipment, an SDRAM controller based on ping-pong operation is designed as the test equipment data buffer. This paper introduces the FPGA-based design of the master, including the SDRAM internal interface design, data transmission and ping-pong operation. The image data is sent to the test bus through the image generating device to verify the function of the controller. The data read / write rate is stable up to 125 Mbit / s, which proves that the controller has good performance and can meet the needs of multi-bus ground test equipment.