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扰码是在数字传输系统中,对于数字信息进行随机化处理的一种技术,被广泛应用于通信各个领域。首先介绍了扰码和自同步扰码的基本原理,通过对扰码原理的分析,实现了一种任意特征多项式、任意N位并行自同步扰码算法,并可演算得到任意特征多项式、任意N位并行帧同步扰码算法。该方法采用递推的方法直接得出N个时钟周期后编码器的状态值与当前编码器状态值之间的逻辑关系。其逻辑运算速度快且实现简单,十分有利于硬件实现。然后研究了基于802.3ba未来100G以太网中640bits自同步扰码算法的FPGA实现,给出了组合逻辑实现和时序逻辑实现两种方案,并对两种方案进行了对比分析,最后给出了640bits并行扰码器实现资源需求分析。
Scrambling code is a technique for randomizing digital information in digital transmission systems and is widely used in various fields of communication. Firstly, the basic principle of scrambling code and self-synchronizing scrambling code is introduced. By analyzing the principle of scrambling code, an arbitrary characteristic polynomial and arbitrary N-bit parallel self-synchronizing scrambling algorithm are realized, and any characteristic polynomial can be calculated and any N Bit parallel frame synchronization scrambling algorithm. The method uses the recursive method to directly obtain the logical relationship between the encoder state value and the current encoder state value after N clock cycles. Its logical operation speed and easy to implement, is very conducive to hardware. Then we study the FPGA implementation of 640bits self-synchronization scrambling algorithm based on 802.3ba 100G Ethernet in the future, and present two schemes of combinatorial logic implementation and sequential logic implementation, and compare and analyze the two schemes. Finally, Parallel scrambler to achieve resource needs analysis.