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Among the components on a many-core chip, network-on-chip(No C) has already contributed a large portion to overall power consumption. Optimizing No C performance under a given power budget is further complicated to keep the network connectivity and minimize the detour distances. In this paper, a No C power budgeting method from the communication perspective is proposed, which intelligently powers off routers/links and sets up alternative paths to restrict the power and thermal envelop. The effect of performance optimizaion of the proposed power budgeting mothod is measured based on latency and in the given power budget, 22% latency can be reduced averagely compared with some competing methods when running real benchmarks.
Among the components on a many-core chip, network-on-chip (No C) has already contributed a large portion to overall power consumption. Optimizing No C performance under a given power budget is further complicated to keep the network connectivity and minimize the In this paper, a No C power budgeting method from the communication perspective is proposed, which intelligently powers off routers / links and sets up alternative paths to restrict the power and thermal envelop. The effect of performance optimizaion of the proposed power budgeting mothod is measured based on latency and in the given power budget, 22% latency can be reduced averagely compared with some competing methods when running real benchmarks.