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为了推广开关电流电路技术（ＳＩ）的应用，引用了新型的两步采样开关电流技术（Ｓ２Ｉ），对该电路中减小时钟馈漏效应的几种方法进行了分析。利用差分平衡结构的Ｓ２Ｉ存储单元设计了平衡Ｓ２Ｉ积分器，并在此基础上设计出一种平衡差分结构的二阶ΣΔ调制器。该调制器能够完全与标准ＣＭＯＳ数字工艺兼容。利用标准１．２μｍ数字ＣＭＯＳ工艺的ＨＳＰＩＣＥ模型参数进行模拟，并用ＭＡＴＬＡＢ对ＨＳＰＩＣＥ输出结果进行了分析，验证了ΣΔ调制器的功能。
In order to promote the application of switching current circuit (SI) technology, a new two-step sampling switch current technology (S2I) is introduced and several methods to reduce the clock feed-through effect in this circuit are analyzed. A balanced S2I integrator is designed by using S2I memory cells with differential balance structure. On the basis of this, a second order ΣΔ modulator with balanced differential structure is designed. The modulator is fully compatible with standard CMOS digital processes. The HSPICE model parameters of the standard 1.2μm digital CMOS process were simulated and the output of HSPICE was analyzed by MATLAB to verify the function of ΣΔ modulator.