提出一种基于二分输出排队的新型 ATM交换结构 ,在现有工艺水平下 ,能够大幅度降低存储器和总线的操作速度 ,在降低实现成本的同时 ,仍然保持了同基本输出排队结构相同时延性能以及时分交换机的多播功能 ,从而提高时分交换机的容量 . A novel ATM switching architecture based on binary output queuing is proposed, which can greatly reduce the operating speed of memory and bus under the current technology level. While reducing the implementation cost, it still maintains the same delay performance as the basic output queuing structure As well as the time division switch multicast capabilities, thereby increasing the capacity of the time switch.