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本文叙述了一纯数字式锁相环路。此环路的输出是一个等于输入脉冲频率好几倍的脉冲频率,并与该输入脉冲频率同步。本文还分析了该环路的稳定性条件。
This article describes a pure digital phase-locked loop. The output of this loop is a pulse frequency several times the input pulse frequency, synchronized with the input pulse frequency. The paper also analyzes the stability of the loop conditions.