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为了实现RSA公钥加密处理的高速化,本文提出了一种采用SD(Signed—Digit)数运算的,适合于LSI处理的多值硬件算法在RSA加密处理中,必须进行字长特别长的运算。本算法由于采用了四进制SD数体制来反复进行加法运算,因而可以进行高速处理。另外,根据本算法还提出了采用微程序控制方式的,适用于LSI的加密处理器的设计方法,为了从原理上论证该处理器,还采用二值TTL逻辑元件试制出了实现16比特加密处理的处理器样品。而且,以2μmCMOSLSI为前提,应用电子线路分析程序SPICE2对采用本算法设计出的加密处理LSI进行模拟,从而对其进行了综合评价。在处理字长为512比特的消息时,加密速度为60千比特/秒,与采用同样方法的二进制数算法相比较,运算速度可以提高八倍以上。除此之外,由于在该处理器中采用了大约十万个晶体管,因此,可以完全地集成在一块芯片上。
In order to speed up RSA public key encryption processing, a multi-value hardware algorithm that is suitable for LSI processing using SD (Signed-Digit) operation is proposed. In the RSA encryption processing, an extra long word length operation is required . The algorithm as a result of a system of four-digit SD repeated addition operations, which can be high-speed processing. In addition, according to this algorithm, a design method of the encryption processor suitable for LSI based on the micro-program control method is also proposed. In order to demonstrate the processor in principle, a binary TTL logic element is also used to manufacture a 16-bit encryption processing Processor sample. In addition, based on the CMOSOSLSI of 2μm, the electronic circuit analysis program SPICE2 was used to simulate the encryption processing LSI designed by this algorithm. When dealing with messages with a word size of 512 bits, the encryption rate is 60 kilobits per second, which can be up to eight times faster than binary arithmetic using the same method. In addition, due to the processor used in about 100,000 transistors, so it can be fully integrated in a chip.