为了缓解随处理器核数增多而被激化的“存储墙”问题,提出了局部高速交叉互连、全局片上网络互连的两级混合互连网络结构,设计了支持统一编址方式的数据传送机制.在现场可编程门阵列上实现了2种规模的存储结构,对面积、时序和功耗进行统计.基于System C开发了混合仿真平台,仿真结果表明,所提结构具有较高的存储访问带宽和较低的局部数据访问延迟. In order to alleviate the “storage wall” problem that is exacerbated with the increase of processor cores, a two-stage hybrid interconnection network structure with local high-speed cross-interconnection and global on-chip network interconnection is proposed. Data transmission mechanism.On the field programmable gate array, two kinds of storage structures are realized, and the area, timing and power consumption are calculated.The mixed simulation platform is developed based on System C. The simulation results show that the proposed structure has higher Storage access bandwidth and lower local data access latency.