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设计了一种内置差分信号有效性检测电路的串行低压差分信号接收器,通过对信号的差分摆幅进行比较,能够正确检测差分信号是否处于标准范围之内。采用片内阻抗匹配网络和镜像补偿型差分电路结构实现了高速串行差分信号到CMOS电平信号的转换,也克服了高速信号传输过程中的信号完整性问题。基于0.13μm CMOS混合信号工艺设计,仿真结果表明,所设计的电路能够正确检测和接收数据率高达2.5 Gb/s,差分摆幅超过200 mV的串行差分信号。
A serial low-voltage differential signal receiver with a built-in differential signal validity detection circuit is designed. By comparing the differential amplitude of the signals, it is possible to correctly detect whether the differential signal is within the standard range. The conversion of high speed serial differential signal to CMOS level signal is realized by the on-chip impedance matching network and mirror compensated differential circuit structure, and the problem of signal integrity in high-speed signal transmission is also overcome. Based on the 0.13μm CMOS mixed-signal process design, simulation results show that the designed circuit can correctly detect and receive serial differential signals with data rates up to 2.5 Gb / s and differential swing over 200 mV.