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为高速通信系统,研制一套单片逻辑系列。已研制的系列能够提供8微微焦耳的速度与功耗乘积,2千兆赫的翻转频率以及在50欧姆传输系统里,传播延迟时间为400微微秒/门。实现高速低功耗的首要因素是新的电路形式:改进的无阈值逻辑(N.T.L)电路。在该电路里,晶体管几乎是工作在作用区域,因此提高了开关速度。此外,为了使触发器的传播延迟时间近似等于一个门电路的延迟,设计了一种新型的主从触发器。器件制造采用p-n结隔离,晶体管的射极条宽是2微米,截止频率是4千兆赫。本文叙述已研制的逻辑系列的性能与电路设计。
For high-speed communications systems, development of a single logic series. The family has been developed to provide 8 joules of speed and power consumption products, 2 gigahertz turnover frequency and 50 ohm transmission system, the propagation delay time of 400 pico-second / door. The primary factor in achieving high speed and low power consumption is the new circuit form: Improved No Threshold Logic (N.T.L) circuit. In this circuit, the transistor operates almost in the area of action, thus increasing the switching speed. In addition, a new master-slave flip-flop is designed to make the delay of the flip-flop approximately equal to the delay of a gate. The device is fabricated using p-n junction isolation. The emitter emitter width of the transistor is 2 μm and the cut-off frequency is 4 GHz. This article describes the logic series has been developed performance and circuit design.