论文部分内容阅读
设计了一款基于CMOS工艺的高动态范围宽带I/Q解调器。该解调器电路包括射频V/I转换电路、混频电路、中频缓冲电路,并且内部集成了高性能I/Q信号产生电路。此外,该解调器可以通过电流调控引脚对芯片工作电流进行调整从而实现三阶交调截取点和噪声系数的折中。该电路本振、射频端口可以工作在0.7-2.7 GHz范围内,在2.7 GHz工作频率下,输入三阶截点为26 dBm,噪声系数15.5 dB,1 dB压缩点输入功率为10.3 dBm。在5 V电源电压下,电流调控引脚悬空,芯片使能端有效的条件下,芯片工作电流为227 mA。该I/Q解调器电路采用0.35μm CMOS工艺设计,芯片面积约为3.8 mm2。
A high dynamic range wideband I / Q demodulator based on CMOS technology was designed. The demodulator circuit includes a radio frequency V / I conversion circuit, a mixer circuit, an intermediate frequency buffer circuit, and a high-performance I / Q signal generation circuit integrated therein. In addition, the demodulator can adjust the operating current of the chip through the current regulation pin to achieve the compromise between the third-order intercept point and the noise figure. The LO and RF ports of the circuit can work in the range of 0.7-2.7 GHz. The input third-order cut-off point is 26 dBm and the noise figure is 15.5 dB at 2.7 GHz. The input power of the 1 dB compression point is 10.3 dBm. Under the 5 V supply voltage, the current regulation pin is left floating, and the chip enables the chip to work at 227 mA while the enable bit is enabled. The I / Q demodulator circuit using 0.35μm CMOS process design, the chip area of about 3.8 mm2.